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Deliverable 5.3: Fault Stress Analysis of HVDC Circuit Breakers

This deliverable provides a fault stress analysis of HVDC circuit breakers within Work Package 5, which looks at the test environment of HVDC circuit breakers.

In order to realize multi-terminal, meshed HVDC networks (MTDC), considerable research and development to effectively reduce the risks associated with the viability of these technologies, both on component as well as system level, is underway. Before putting these research results into practical applications, appropriate testing of these developments is crucial. Hence, to accelerate the realization of the envisaged MTDC networks, test facilities sufficiently representing a practical DC system under various conditions need to be designed and developed.

This deliverable provides a fault stress analysis of HVDC circuit breakers within Work Package 5, which looks at the test environment of HVDC circuit breakers.

To date no HVDC circuit breakers have been applied in real HVDC systems. Due to the absence of practical experience with such devices, discussions about their implementation mostly remain theoretical. As a result, the state-of-development, abilities and limitations of HVDC circuit breakers and the impact of their operation on a HVDC network, both adverse and beneficially, are not well understood by their prospective end users. This uncertainty, along with economic considerations, impedes the uptake of HVDC circuit breakers and thus, in part, prevents the realization of meshed multi-terminal networks.

So far there are no clearly specified and quantified requirements of HVDC circuit breakers, let alone a standardized method to test these devices. The main objective in the report is, therefore, to gain sufficient insight into the requirements of HVDC circuit breakers by embedding their simulation model in a multi-terminal HVDC study grid. For this purpose, two main categories of HVDC circuit breakers; namely, mechanical active current injection and hybrid between mechanical and power electronic technologies of are modeled and inserted into a multi-terminal benchmark study grid. The fault current interruption process and the associated stresses with each circuit breaker technology during the interruption process are investigated in detail via simulation studies.

Finally, the report concludes by translating the stresses obtained from simulation studies into the test requirements that a test circuit should replicate in order to adequately test the HVDC circuit breakers as in operation.